Raw Interrupt Status Register
| RORRIS | This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. |
| RTRIS | This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). |
| RXRIS | This bit is 1 if the Rx FIFO is at least half full. |
| TXRIS | This bit is 1 if the Tx FIFO is at least half empty. |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |